The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor device with a silicide region.
As the semiconductor industry has progressed into nanometer technology nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a gate-all-around (GAA) transistor. A typical GAA transistor enables enhanced control of the charge carriers along the lengthwise direction through a complete encirclement of the channel region of a semiconductor nanowire by a gate dielectric and a gate electrode. The GAA transistor has a reduced short channel effect, because the channel region may be surrounded by the gate electrode so that an effect of the source/drain region on an electric field of the channel region may be reduced.
However, there are challenges to implementation of such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, less silicide formation on source region causes high contact resistance of source regions of the GAA transistor, thereby degrading the device performance.